module IDEXE(	CLK, nop, reset,
		instruction_in, instruction_out,
		pc_in, pc_out,

		reg1_in, reg1_out, reg2_in, reg2_out, reg3_in, reg3_out,

		reg_wen_in, reg_wen_out,
		wb_sel_in, wb_sel_out,
		reg_waddr_in, reg_waddr_out,

		mem_wen_in, mem_wen_out,
		isjeq_in, isjeq_out,
		isjlt_in, isjlt_out,

		aluop_in, aluop_out,
		alusrc2_sel_in, alusrc2_sel_out,
		aluimm_in, aluimm_out
		);

   input CLK;
   input reset;
   input nop;
   input [31:0] instruction_in;
   reg [31:0]   instruction;
   output [31:0] instruction_out;
   assign instruction_out = instruction;

   input [31:0]  pc_in;
   reg [31:0]    pc;
   output [31:0] pc_out;
   assign pc_out = pc;

   input [31:0]  reg1_in;
   reg [31:0]    reg1;
   output [31:0] reg1_out;
   assign reg1_out = reg1;

   input [31:0]  reg2_in;
   reg [31:0]    reg2;
   output [31:0] reg2_out;
   assign reg2_out = reg2;

   input [31:0]  reg3_in;
   reg [31:0]    reg3;
   output [31:0] reg3_out;
   assign reg3_out = reg3;
   //----------------------------------
   input         reg_wen_in;
   reg           reg_wen;
   output        reg_wen_out;
   assign reg_wen_out = reg_wen;

   input         wb_sel_in;
   reg           wb_sel;
   output        wb_sel_out;
   assign wb_sel_out = wb_sel;

   input [4:0]   reg_waddr_in;
   reg [4:0]     reg_waddr;
   output [4:0]  reg_waddr_out;
   assign reg_waddr_out = reg_waddr;
   //----------------------------------
   input         mem_wen_in;
   reg           mem_wen;
   output        mem_wen_out;
   assign  mem_wen_out = mem_wen;

   input         isjeq_in;
   reg           isjeq;
   output        isjeq_out;
   assign  isjeq_out = isjeq;

   input         isjlt_in;
   reg           isjlt;
   output        isjlt_out;
   assign  isjlt_out = isjlt;
   //----------------------------------
   input [3:0]   aluop_in;
   reg [3:0]     aluop;
   output [3:0]  aluop_out;
   assign aluop_out = aluop;

   input         alusrc2_sel_in;
   reg           alusrc2_sel;
   output        alusrc2_sel_out;
   assign  alusrc2_sel_out = alusrc2_sel;


   input [15:0]  aluimm_in;
   reg [15:0]    aluimm;
   output [15:0] aluimm_out;
   assign aluimm_out = aluimm;

   //-----------------------------------

   always@(posedge CLK or posedge reset)
     begin
        if (reset) begin
	   pc   	<= 0;
    	   instruction <= 0;
    	   reg1 	<= 0;
    	   reg2 	<= 0;
    	   reg3 	<= 0;

    	   reg_wen <= 0;
    	   wb_sel 	<= 0;
    	   reg_waddr<=0;

    	   mem_wen <= 0;
    	   isjeq 	<= 0;
    	   isjlt   <= 0;

    	   aluop   <= 0;
    	   alusrc2_sel <= 0;
    	   aluimm   <= 0;
        end else if (nop) begin
	   pc   	<= pc_in;
    	   instruction <= 0;
    	   reg1 	<= reg1_in;
    	   reg2 	<= reg2_in;
    	   reg3 	<= reg3_in;

    	   reg_wen <= 0;
    	   wb_sel 	<= wb_sel_in;
    	   reg_waddr<=reg_waddr_in;

    	   mem_wen <= 0;
    	   isjeq 	<= 0;
    	   isjlt   <= 0;

    	   aluop   <= aluop_in;
    	   alusrc2_sel <= alusrc2_sel_in;
    	   aluimm   <= aluimm_in;

    	end else begin
	   pc   	<= pc_in;
    	   instruction <= instruction_in;
    	   reg1 	<= reg1_in;
    	   reg2 	<= reg2_in;
    	   reg3 	<= reg3_in;

    	   reg_wen <= reg_wen_in;
    	   wb_sel 	<= wb_sel_in;
    	   reg_waddr<=reg_waddr_in;

    	   mem_wen <= mem_wen_in;
    	   isjeq 	<= isjeq_in;
    	   isjlt   <= isjlt_in;

    	   aluop   <= aluop_in;
    	   alusrc2_sel <= alusrc2_sel_in;
    	   aluimm   <= aluimm_in;
    	end

     end


endmodule
